SETCLR1=SET_AND_CLEAR_DO_NOT, SETCLR3=SET_AND_CLEAR_DO_NOT, SETCLR0=SET_AND_CLEAR_DO_NOT, SETCLR2=SET_AND_CLEAR_DO_NOT
SCT output counter direction control register
| SETCLR0 | Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. 0 (SET_AND_CLEAR_DO_NOT): Set and clear do not depend on any counter. 1 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter L or the unified counter is counting down. 2 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. |
| SETCLR1 | Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. 0 (SET_AND_CLEAR_DO_NOT): Set and clear do not depend on any counter. 1 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter L or the unified counter is counting down. 2 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. |
| SETCLR2 | Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. 0 (SET_AND_CLEAR_DO_NOT): Set and clear do not depend on any counter. 1 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter L or the unified counter is counting down. 2 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. |
| SETCLR3 | Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. 0 (SET_AND_CLEAR_DO_NOT): Set and clear do not depend on any counter. 1 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter L or the unified counter is counting down. 2 (SET_AND_CLEAR_ARE_RE): Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. |
| RESERVED | Reserved |